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| Gigabit Ethernet: 1.25 GBd 1300 nm Laser Transceiver in Low Cost 1 x 9 Package Style Preliminary Technical Data HFCT-5305 Features * Compliant with Proposed Specifications for IEEE802-3 Gigabit Ethernet * 1300 nm Trenched BH Laser Source Technology * Industry Standard 1 x 9 Package Style with Integral Duplex SC Connector * Class 1 Laser Safety (Certification Pending) * 3 km Links in 8/125 m SMF Cables * 550 m Links in 62.5/125 m MMF Cables * Single +5 V Power Supply Operation and PECL Logic Interfaces * Wave Solder and Aqueous Wash Process Compatible * Designed and Manufactured in an ISO 9000 Certified Facility Description General Transmitter Section The transmitter section consists of a 1300 nm Laser in an eye safe optical subassembly, (ELSA), which mates to the fiber cable. The ELSA is driven by a custom silicon bipolar IC which converts differential PECL logic signals, ECL referenced to a +5 V supply, into an analog Laser Diode drive current. Eye Safety Design The ELSA is designed to be eye safe under a single fault condition. To be eye-safe, only one of two results can occur in the event of a single fault. The transmitter must either maintain a safe level of output power or the transmitter should be disabled. The ELSA contains a patented optical fiber stub which restricts the level of light emerging from the connector port under all conditions. Overdriving the laser (even to destruction) cannot produce enough light to violate the IEC safe level. As a result the HFCT-5305 is intrinsically eye safe. Receiver Section The receiver includes an InP PIN photodiode mounted together with a custom silicon bipolar transimpedance preamplifier IC in an optical subassembly, OSA. This OSA is mated to a custom silicon bipolar circuit providing post-amplification and quantization. The custom silicon bipolar circuit also includes a Signal Detect circuit which provides a PECL logic high output upon detection of a usable input optical signal level. This single-ended lowpower PECL output is designed to drive a standard PECL input Applications * Host to Host Interface Preliminary Product Disclaimer This preliminary data sheet is provided to assist you in the evaluation of engineering samples of the product which is under development and targeted for release during 1997. Until Hewlett-Packard releases this product for general sales, HP reserves the right to alter prices, specifications, features, capabilities, function, manufacturing release dates, and even general availability of the product at any time. (5/97) 565 through a 10 load instead of the normal 50 ECL load. Regulatory Compliance See the Regulatory Compliance Table for the targeted typical and measured performance for these transceivers. As the product design is completed, full characterization testing will be done to determine the actual performance of the final design. The overall equipment design will determine the level it is able to be certified to. These transceiver performance targets are offered as a figure of merit to assist the designer in considering their use in equipment designs. Electrostatic Discharge (ESD) There are two design cases in which immunity to ESD damage is important. The first case is during handling of the transceiver prior to mounting it on the circuit board. It is important to use normal ESD handling precautions for ESD sensitive devices. These precautions include using grounded wrist straps, work benches, and floor mats in ESD controlled areas. The targeted performance has been shown to provide adequate performance typical industry production environments. The second case to consider is static discharges to the exterior of the equipment chassis containing the transceiver parts. To the extent that the duplex SC connector is exposed to the outside of the equipment chassis it may be subject to whatever system level ESD test criteria that the equipment is intended to meet. The targeted performance is more robust than typical industry equipment practices today. Electromagnetic Interference (EMI) Most equipment designs utilizing these high speed transceivers from Hewlett-Packard will be required to meet the requirements of FCC in the United States, CENELEC EN55022 (CISPR 22) in Europe and VCCI in Japan. These transceivers, with their shielded design, are targeted to perform to the limits listed to assist the designer in the management of the overall equipment EMI performance. Immunity Equipment utilizing these transceivers will be subject to radio-frequency electromagnetic fields in some environments. Regulatory Compliance Feature Test Method Electrostatic Discharge MIL-STD-883C (ESD) to the Method 3015.4 Electrical Pins Electrostatic Discharge Variation of IEC 801-2 (ESD) to the Duplex SC Receptacle Electromagnetic Interference (EMI) Targeted Performance Class 1 (>500 V) Immunity Eye Safety Products of this type will typically withstand at least 25 kV without damage when the Duplex SC Connector Receptacle is contacted by a Human Body Model probe. FCC Class A Typically provide a TBD dB margin to the noted CENELEC EN55022 Class A standard limits when tested at a certified test (CISPR 22A) range with the transceiver mounted to a circuit VCCI Class I card without a chassis enclosure. Variation of IEC 801-3 Typically show no measurable effect from a 3 V/m field swept from 10 to 450 MHz applied to the transceiver without a chassis enclosure. FDA CDRH 21-CFR 1040 Class Compliant per Hewlett-Packard Testing for all 1 IEC 825 Issue 1 1993: three requirements under normal operating 11 Class conditions. Fault condition testing pending 1 CENELEC EN60825 Class 1 completion of product development. 566 These transceivers have an immunity to such fields due to their shielded design. Eye Safety These 1300 nm Laser-based transceivers are intended to provide Class 1 eye safety by design. Hewlett-Packard has tested the current transceiver design for compliance with the requirements listed below under normal operating conditions and will test for compliance under fault conditions when the product design is completed. HP will obtain certification from outside sources for eye safety. This performance will enable the transceivers to be used without concern for eye safety in the same way that LED-based transceivers are used today. Absolute Maximum Ratings Parameter Storage Temperature Ambient Operating Temperature Supply Voltage Data Input Voltage Transmitter Differential Input Voltage Symbol TS TA VCC VI VD Min. -40 -10 -0.5 -0.5 See Table Below Typ. Max. +100 +80 7 VCC 1.4 Unit C C V V V Reference 1 Recommended Operating Conditions Parameter Symbol Min. Typ. Ambient Operating Temperature TA 0 Relative Humidity RH 5 Supply Voltage VCC 4.75 Power Supply Ripple Power Supply Rejection Transmitter Data Input Voltage - Low VIL-VCC -1.810 Transmitter Data Input Voltage - High VIH-VCC -1.165 Transmitter Differential Input Voltage VD 0.3 Data Output Load RDL 50 Signal Detect Output Load RSDL 7 10 Conducted Noise on Data and Signal TBD Detect Outputs Max. Unit +70 C 95 % 5.25 V TBD Hz/Vpp TBD Hz/Vpp -1.475 V -0.880 V See Table Above V Hz/Vpp Reference 2 2 3 4 Process Compatibility Parameter Hand Lead Soldering Temperature/Time Wave Soldering and Aqueous Wash Symbol TSOLD/tSOLD TSOLD/tSOLD Min. Typ. Max. +270/10 +270/10 Unit C/sec. C/sec. Reference Notes: 1. This is the maximum voltage that can be applied across the Differential Transmitter Data Inputs without damaging the ESD protection circuit. 2. Compatible with 10 K, 10 KH and 100 K ECL and PECL signals. 3. The outputs are terminated to VCC - 2 V. 4. The outputs are terminated to ground. 567 Transmitter Electrical Characteristics (TA = 0C to +70C, VCC = 4.75 V to 5.25 V) Parameter Symbol Supply Current ICCT Power Dissipation PDIST Data Input Current - Low IIL Data Input Current - High IIH Min. Typ. 65 0.35 0 16 Max. 130 0.68 350 Unit mA W A A Reference 5 -350 Receiver Electrical Characteristics (TA = 0C to +70C, VCC = 4.75 V to 5.25 V) Parameter Symbol Supply Current ICCR Power Dissipation PDISR Data Output Voltage - Low VOL - VCC Data Output Voltage - High VOH - VCC Data Output Rise Time tr Data Output Fall Time tf Signal Detect Output Voltage - Low VOL - VCC Signal Detect Output Voltage - High VOH - VCC Signal Detect Assert Time tSDA (Off to On) Signal Detect Assert Time tSDD (On to Off) Min. Typ. 100 0.4 Max. 120 0.5 -1.620 -0.740 0.51 0.51 -1.620 -0.880 TBD TBD Unit mA W V V ns ns V V s s Reference 6 7 7 8 8 7 7 9 10 -1.950 -1.045 0.2 0.2 -1.840 -1.045 0.3 0.3 Notes: 5. The typical value is at +70C; maximum value is an end of life value. 6. Power dissipation value is the power dissipated in the receiver itself. It is calculated as the sum of the products of VCC and ICC minus the sum of the products of the output voltages and currents. 7. These outputs are compatible with 10 K, 10 KH and 100 K ECL and PECL inputs. 8. These values are under review and may be replaced by an eye mask test. 9. The Signal Detect output will change from logic "0" to "1" within TBD us of a step transition in optical input power from no light to -18 dBm. 10. The Signal Detect output will change from logic "1" to "0" within TBD us of a step transition in optical input power from -16 dBm to no light. 568 Transmitter Optical Characteristics (TA = 0C to +70C, VCC = 4.75 V to 5.25 V) Parameter Symbol Output Optical Power PO 62.5/125 m, NA = 0.275 fiber Optical Extinction Ratio Center Wavelength C Spectral Width - rms RIN12 Min. -13 9 1270 Typ. Max. -3 Unit dBm avg. dB nm nm rms dB/Hz Reference 1355 4 -116 Receiver Optical Characteristics (TA = 0C to +70C, VCC = 4.75 V to 5.25 V) Parameter Symbol Min. Input Optical Power PIN -3 Minimum Return Loss 12 Signal Detect - Asserted PA PD + 1.5 dB Signal Detect - Deasserted PD -45 Signal Detect - Hysteresis PA - PD 1.5 Note: 11. The sensitivity is provided at a BER of 1 x 10-12. Typ. Max. -20 Unit dBm avg. dB dBm avg. dBm avg. dB Reference 11 569 Table 1. Pinout Table Pin Symbol Mounting Studs Functional Description The mounting studs are provided for transceiver mechanical attachment to the circuit board, they are embedded in the nonconductive plastic housing and are not tied to the transceiver internal circuit. They should be soldered into plated-through holes on the printed circuit board. Receiver Signal Ground Directly connect this pin to receiver signal ground plane. Receiver Data Out See recommended circuit schematic. Receiver Data Out Bar See recommended circuit schematic. Signal Detect Normal optical input levels to the receiver result in a logic "1" output. Low optical input levels to the receiver result in a fault condition indication shown by a logic "0" output. Signal Detect is a single-ended, low-power, PECL output. Since SD is a low-power PECL output, complete the interconnection of SD output with other PECL inputs using a 10 k pull-down resistor to VEE to allow biasing of this interconnection. Do not load this SD output with standard PECL, 50 to VCC - 2 V, termination. If Signal Detect output is not used, leave it open-circuited. This Signal Detect output can be used to drive a PECL input on an upstream circuit, such as, Signal Detect input or Loss of Signal-bar. Receiver Power Supply Provide +5 V dc via the recommended transmitter power supply filter circuit. Locate the power supply filter circuit as close as possible to the VCCR pin. Transmitter Power Supply Provide +5 V dc via the recommended transmitter power supply filter circuit. Locate the power supply filter circuit as close as possible to the VCCT pin. Transmitter Data In Bar See recommended circuit schematic. Transmitter Data In See recommended circuit schematic. Transmitter Signal Ground Directly connect this pin to the transmitter signal ground plane. 1 2 3 4 VEER RD+ RD- SD 5 VCCR 6 VCCT 7 8 9 TD- TD+ VEET RECEIVER SIGNAL GROUND RECEIVER DATA OUT RECEIVER DATA OUT BAR SIGNAL DETECT RECEIVER POWER SUPPLY TRANSMITTER POWER SUPPLY TRANSMITTER DATA IN BAR TRANSMITTER DATA IN TRANSMITTER SIGNAL GROUND 1 2 3 4 5 6 7 8 9 TOP VIEW N/C N/C Figure 1. Pinout. 570 A B C AREA RESERVED FOR PROCESS PLUG D F E K (8 x 2.54 mm) G J H DIM. A B C D E F* G H J K MILLIMETERS MIN. TYP. 12.7 25.4 0.25 2.92 20.32 15.9 20.32 20.32 0.38 3.68 9.8 0.010 0.115 MAX. 39.6 MIN. INCHES TYP. 0.500 1.000 0.015 0.145 0.386 0.800 0.626 0.800 0.800 MAX. 1.559 H *PRE-RELEASE SAMPLES MAY HAVE HEIGHT UP TO 10.35 mm (0.407 INCHES). Figure 2. Package Outline Drawing and Pinout. 571 1 PECL OUTPUT STAGE RD C4 R5 2 RD- C5 R6 3 ELECTRICAL SERIAL OUTPUT RECEIVER CIRCUITRY SD C6 VCC L1 C7 L2 C1 R1 VCC C9 C8 R7 4 5 1 x 9 LASER SERIAL MODULE 6 STAGE TD- 7 INPUT R2 TD C2 C3 R3 8 R4 9 ELECTRICAL SERIAL INPUT LASER DRIVER CIRCUITRY C1 = C2 = C3 = C4 = C5 = 0.01 F C6 = C7 = C8 = C9 = 0.01 F R1 = R3 = 68 R2 = R4 = 192 R5 = R6 = 270 R7 = 10 k L1 = L2 = 1 H Figure 3. Recommended Circuit Schematic. A PECL D DIM. A B C D E MILLIMETERS MIN. - - - 1.8 0.7 TYP. 20.32 20.32 2.54 - - MAX. - - - 2.0 0.9 MIN. INCHES TYP. MAX. - 0.800 - - 0.800 - - 0.100 - 0.071 - 0.079 0.028 - 0.036 B E C TOP VIEW Figure 4. Recommended Board Layout Hole Pattern. 572 |
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